The present invention relates to a semiconductor memory device and, more particularly, to a row decoder in a memory device for driving each of word lines at a plurality of points thereof.
As well known in the art, a memory device includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells disposed at intersections of the word and bit lines, respectively. One of the word lines and one of the bit lines are selected and driven to designate one of memory cells. The selection of the word line is performed by a row decoder in response to row address information. Specifically, the row decoder decodes the content of the row address information and selects and drives one word line to an active level.
In accordance with increase in memory capacity, the word line is prolonged to allow a great number of memory cells to be connected thereto. The stray resistance and capacitance of the word line are thereby made large. For this reason, it would take a relatively long period of time to drive the word line to the active level, if the word line would be driven only at one end thereof by the row decoder. The word line is therefore driven at a plurality of points thereof.
Referring to FIG. 1, a memory device according to a prior art includes a memory cell array portion 10 in which four row decoders 2-1 to 2-4 are provided to drive each of word lines W at four points thereof. A memory cell array is therefore divided into five arrays 1-1 to 1-5. Each of the row decoders 2 is disposed between the adjacent memory cell arrays 1, as shown. In this example, row address information consists of nine bits and therefore 512 word lines W0 to W511 are provided. Each of the memory cell arrays 1 has a plurality of bit lines B, and memory cells MC are disposed on the respective intersections of the word and bit lines.
Turning to FIGS. 2, 26 and there is shown a circuit of the row decoder for the word line W0. Each of the decoders 2 includes an inverter 21 and a 3-input NAND gate 22. The NAND gate 22 receives pre-decoded signals P0-P2 generated by a pre-decoder 25. This decoder 25 includes three inverters 254-256 and three 3-input NAND gates 253-255. These NAND gates 253-255 receive selected ones of true and complementary levels of the nine row address signals. In the illustrated example, the true levels of the nine address signals A0-A8 are supplied. Accordingly, when all the address signals A0-A8 takes the high level, each of the pre-decoded signals P0-P2 take the high levels, so that the word line W0 is selected and driven to the active high level. Since the word line W0 is driven at four points thereof, it is charged up to the active high level in a short period of time.
Referring to FIG. 3, there is shown a memory cell array portion 50 according to another prior art. In this memory, the memory cell array portion 50 is divided into 128 blocks 55-0 to 55-127, and each of the blocks 55 therefore includes four word lines. Each of the blocks 55 further includes a main-row decoder 60. Also in this memory, there are provided four sub-row decoders 61-1 to 61-4 to drive each,of the word lines at four points thereof, and a memory cell array is divided into five cell arrays
Turning to FIG. 4, which illustrates the block 55-1 in more detail, each of the sub-row decoders 61 includes four 2-input NOR gates 611 to drive four word lines W0-W3, respectively. The first input of each NOR gate 611 is connected to the block row decoder 60 comprising an inverter 602 and a 3-input NOR gate 601. This gate 601 receives block pre-decoded signals BP0-BP2 which are generated by a pre-decoder (not shown) in response to seven bits of the row address information in the similar manner to that described with reference to FIG. 2. When all the signals BP0-BP2 take the low level, the output of the block decoder 60 is changed to the active low level to select the block 55-1. The remaining two bits of the row address information is used for selecting one of the four word lines W0-W3. Specifically, the different four combinations of the true and complementary levels of the two row address bits are supplied to four sub-decoders comprising NOR gates 550-553 and inverters 554-557 respectively, as shown. The output of the inverter 554 is supplied in common to the second inputs of the NOR gates 611-21 to 611-31, and for driving the word line W0. Similarly, the outputs of the inverters 555, 556 and 557 are supplied to the corresponding NOR gates 611 for driving the word lines W1-W3, respectively. Thus, when the output of the block decoder 60 takes the active low level and the inverter 554 also takes the active low level, the NOR gates 611-11, 611-21, 611-31 and 611-41 select and drive the word line W0 to the active high level simultaneously with one another. The word line W is thereby charged up to the high level in a short period of time.
Although the memory shown in FIGS. 1 and 2a and 2b and the memory shown in FIGS. 3 and 4 both drive each of the word lines at a high speed, the latter memory is advantageous in the number of circuit elements required than the former memory. More specifically, the memory of FIGS. 1 and 2 requires four inverters and four 3-input NAND gates every word line, and thus 16 inverters and 16 3-input NAND gates are required every four word lines. As a result, 64 N-channel transistors and 64 P-channel transistors are needed every four word lines, if each of the inverters and the 3-input NAND gates are constructed by a complementary MOS circuit. On the other hand, the memory of FIGS. 3 and 4 requires one 3-input NOR gate, one inverter and 16 2-input NOR gates every four word lines, and thus 36 N-channel transistors and 36 P-channel transistors in the case of constructing each gate by a complementary MOS circuit. Thus, the memory shown in FIGS. 3 and 4 are advantageous in both speed and the number of required circuit elements.
However, it is further desired to decrease in number the circuit elements without lowering the drive of each word line in order to further enhance the memory capacity.